View 74HCHCT5555_325686.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT5555 Programmable delay timer with oscillator
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
FEATURES * Positive and negative edge triggered * Retriggerable or non-retriggerable * Programmable delay minimum: 100 ns maximum: depends on input frequency and division ratio * Divide-by range of 2 to 224 * Direct reset terminates output pulse * Very low power consumption in triggered start mode * 3 oscillator operating modes: - RC oscillator - Crystal oscillator - External oscillator * Device is unaffected by variations in temperature and VCC when using an external oscillator * Automatic power-ON reset * Schmitt trigger action on both trigger inputs * Direct drive for a power transistor * Low power consumption in active mode with respect to TTL type timers * High precision due to digital timing * Output capability: 20 mA * ICC category: MSI. APPLICATIONS * Motor control * Attic fan timers * Delay circuits * Automotive applications * Precision timing * Domestic appliances. CI CPD Notes QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay A, B to Q/Q MR to Q/Q RS to Q/Q input capacitance power dissipation capacitance per buffer GENERAL DESCRIPTION The 74HC/HCT5555 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT5555 are precision programmable delay timers which consist of: * 24-stage binary counter * integrated oscillator (using external timing components)
74HC/HCT5555
* retriggerable/non-retriggerable monostable * automatic power-ON reset * output control logic * oscillator control logic * overriding asynchronous master reset (MR).
CONDITIONS CL = 15 pF; VCC = 5 V 24 19 26
TYP. 24 20 28 3.5 36
UNIT ns ns ns pF pF
3.5 notes 1 and 2 23
1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs. CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT5555N 74HC/HCT5555D PACKAGE PINS 16 16 PIN POSITION DIL SO16 MATERIAL plastic plastic CODE SOT38Z SOT109A
September 1993
2
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
PINNING SYMBOL RS RTC CTC A B RTR/RTR Q GND Q S 0 - S3 OSC CON MR VCC PIN 1 2 3 4 5 6 7 8 9 10, 11, 12, 13 14 15 16 DESCRIPTION clock input/oscillator pin external resistor connection external capacitor connection trigger input (positive-edge triggered) trigger input (negative-edge triggered) retriggerable/non-retriggerable input (active HIGH/active LOW) pulse output (active LOW) ground (0 V) pulse output (active HIGH) programmable input oscillator control master reset input (active HIGH) positive supply voltage
handbook, halfpage
74HC/HCT5555
RS R TC C TC A B RTR/ RTR Q GND
1 2 3 4 5 6 7 8
MGA642
16
VCC
15 MR OSC 14 CON 13 S 3
5555
12 S2 11 S1 10 S 0 9 Q
Fig.1 Pin configuration.
handbook, halfpage
X/Y 1 2 4 8 RX CX !G 0
10 11 12 13 2 3 14 1 6 4 5
CTRDIVm [T] Y=0
15
Y = 15
+
16G17 17 & 1 S I=0 V16 R CT = 0 CT = m R 9 7
15
R
MGA643
Fig.2 IEC logic diagram.
September 1993
3
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
2
handbook, full pagewidth
3 C TC
10 S0
11 S1
12 S2
13 S3
1 RS OSC 14 CON
R TC
CP 24 - STAGE COUNTER CD
POWER-ON RESET 15 MR 4A 5B 6 RTR/RTR
MGA644
MONOSTABLE CIRCUITRY
Q9 OUTPUT STAGE Q7
Fig.3 Functional diagram. * Trigger pulse applied input B for negative-edge triggering * Trigger pulse applied to inputs A and B (tied together) for both positive-edge and negative triggering. The Schmitt trigger action in the trigger inputs, transforms slowly changing input signals into sharply defined jitter-free output signals and provides the circuit with excellent noise immunity. The OSC CON input is used to select the oscillator mode, either continuously running (OSC CON = HIGH) or triggered start mode (OSC CON = LOW). The continuously running mode is selected where a start-up delay is an undesirable feature and the triggered start mode is selected where very low power consumption is the primary concern. The start of the programmed time delay occurs when output Q goes HIGH (in the triggered start mode, the previously disabled oscillator will start-up). After the programmed time delay, the flip-flop stages are reset and the output returns to its original state. 4
FUNCTIONAL DESCRIPTION The oscillator configuration allows the design of RC or crystal oscillator circuits. The device can operate from an external clock signal applied to the RS input (RTC and CTC must not be connected). The oscillator frequency is determined by the external timing components (RT and CT), within the frequency range 1 Hz to 4 MHz (32 kHz to 20 MHz with crystal oscillator). In the HCT version the MR input is TTL compatible but the RS input has CMOS input switching levels. The RS input can be driven by TTL input levels if RS is tied to VCC via a pull-up resistor. The counter divides the frequency to obtain a long pulse duration. The 24-stage is digitally programmed via the select inputs (S0 to S3). Pin S3 can also be used to select the test mode, which is a convenient way of functionally testing the counter. The "5555" is triggered on either the positive-edge, negative-edge or both. * Trigger pulse applied to input A for positive-edge triggering September 1993
An internal power-on reset is used to reset all flip-flop stages. The output pulse can be terminated by the asynchronous overriding master reset (MR), this results in all flip-flop stages being reset. The output signal is capable of driving a power transistor. The output time delay is calculated using the following formula (minimum time delay is 100 ns): 1 -- x division ratio (s). fi
Once triggered, the output width may be extended by retriggering the gated, active HIGH-going input A or the active LOW-going input B. By repeating this process, the output pulse period (Q = HIGH, Q = LOW) can be made as long as desired. This mode is selected by RTR/RTR = HIGH. A LOW on RTR/RTR makes, once triggered, the outputs (Q, Q) independent of further transitions of inputs A and B.
ndbook, full pagewidth
CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD
September 1993
CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q CD CP Q
C TC
R TC
Philips Semiconductors
RS
OSC CON
S3
S2
S1
S0
Programmable delay timer with oscillator
5
VCC CP CD
MGA655
Q
MR
RTR/RTR
Q
A Q
B
74HC/HCT5555
Product specification
Fig.4 Logic diagram.
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
TEST MODE
74HC/HCT5555
Set S3 to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S0, S1 and S2 to a logic HIGH level, this programs the counter to divide-by 28 (256). Apply a trigger pulse and clock in 255 pulses, this sets all flip-flop stages to a logic HIGH level. Set S3 to a logic HIGH level, this causes the counter to divide-by 224. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 224 (16 777 216) clock pulses. FUNCTION TABLE INPUTS MR H L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH transition = HIGH-to-LOW transition. A X X B X X Q L one HIGH level output pulse one HIGH level output pulse OUTPUTS Q H one LOW level output pulse one LOW level output pulse
September 1993
6
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
DELAY TIME SELECTION SELECT INPUTS S3 L L L L L L L L . H H H H H H H H S2 L L L L H H H H . L L L L H H H H S1 L L H H L L H H . L L H H L L H H S0 L H L H L H L H . L H L H L H L H 21 22 23 24 25 26 27 28 . 217 218 219 220 221 222 223 224
74HC/HCT5555
OUTPUT Q/Q (FREQUENCY DIVIDING) BINARY 2 4 8 16 32 64 128 256 . 131 072 262 144 524 288 1 048 576 2 097 152 4 194 304 8 388 608 16 777 216 DECIMAL
1
handbook, full pagewidth RS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MR
A
Q
MGA649
Timing example shown for S3, S2, S1, S0 = 0011 (binary 24, decimal 16).
Fig.5 Timing diagram.
September 1993
7
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI. DC CHARACTERISTICS FOR 74HC Tamb (C) SYMBOL VOH PARAMETER +25 MIN TYP MAX HIGH level output voltage Q and Q outputs HIGH level output voltage Q and Q outputs HIGH level output voltage Q and Q outputs LOW level output voltage Q and Q outputs LOW level output voltage Q and Q outputs LOW level output voltage Q and Q outputs HIGH level input voltage RS input LOW level input voltage RS input 1.9 4.4 5.9 2 4.5 6.0 - - - -40 to +85 MIN MAX 1.9 4.4 5.9 - - - -40 to +125 MIN 1.9 4.4 5.9 3.7 5.2 MAX - - - - - V V V V V UNIT VCC (V) 2.0 4.5 6.0 4.5 6.0
74HC/HCT5555
TEST CONDITION VI OTHER Io = -20 A
VOH
3.98 4.32 - 5.48 5.81 -
3.84 - 5.34 -
Io = -6.0 mA Io = -7.8 mA
VOH
3.3 4.8
- -
- -
3 4.5
- -
2.7 4.2
- -
V V
4.5 6.0
Io = -20 mA Io = -20 mA
VOL
- - - - -
0 0 0
0.1 0.1 0.1
- - - - -
0.1 0.1 0.1 0.33 0.33
- - - - -
0.1 0.1 0.1 0.40 0.40
V V V V V
2.0 4.5 6.0 4.5 6.0
Io = 20 A
VOL
0.15 0.26 0.15 0.26
Io = 6.0 mA Io = 7.8 mA
VOL
- -
- -
0.9 0.9
- -
1.14 1.14
- -
1.34 1.34
V V
4.5 6.0
Io = 20 mA Io = 25 mA
VIH
1.7 3.6 4.8 - - -
- - - - - -
- - - 0.3 0.9 1.2
1.7 3.6 4.8 - - -
- - - 0.3 0.9 1.2
1.7 3.6 4.8 - - -
- - - 0.3 0.9 1.2
V V V V V V
2 4.5 6.0 2.0 4.5 6.0
VIL
September 1993
8
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
Tamb (C) SYMBOL VOH PARAMETER +25 MIN TYP MAX HIGH level output voltage RTC output 3.98 - 5.48 - 3.98 - 5.48 - - - - - -40 to +85 MIN MAX 3.84 - 5.34 - 3.84 - 5.34 - -40 to +125 MIN 3.7 5.2 3.7 5.2 MAX - - - - V V V V UNIT VCC (V) 4.5 6.0 4.5 6.0
TEST CONDITION VI RS = GND; OSC CON = VCC RS = VCC; OSC CON = GND; untriggered RS = VCC; OSC CON = VCC RS = VCC; OSC CON = GND; untriggered RS = VIH; OSC CON = VIH RS = VCC; OSC CON = VCC RS = VCC; OSC CON = VCC RS = VIL; OSC CON = VIL; untriggered OTHER Io = -2.6 mA Io = -3.3 mA Io = -0.65 mA Io = -0.85 mA
1.9 4.4 5.9 1.9 4.4 5.9 VOH HIGH level output voltage CTC output LOW level output voltage RTC output
2.0 4.5 6 2.0 4.5 6.0
- - - - - - - - 0.26 0.26 0.1 0.1 0.1 0.26 0.26
1.9 4.4 5.9 1.9 4.4 5.9
- - - - - -
1.9 4.4 5.9 1.9 4.4 5.9 3.7 5.2 - - - - - - -
- - - - - - - - 0.4 0.4 0.1 0.1 0.1 0.4 0.4
V V V V V V V V V V V V V V V
2.0 4.5 6.0 2 4.5 6.0 4.5 6.0 4.5 6 2.0 4.5 6 4.5 6.0
Io = -20 A
Io = -20 A
3.98 - 5.48 - - - - - - - - 0 0 0 - -
3.84 - 5.34 - - - - - - - - 0.33 0.33 0.1 0.1 0.1 0.33 0.33
Io = -3.2 mA Io = -4.2 mA Io = 2.6 mA Io = 3.3 mA Io = 20 A
VOL
VOL
LOW level output voltage CTC output
- -
Io = 3.2 mA Io = 4.2 mA
September 1993
9
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER MIN tPLH/tPHL propagation delay A, B to Q, Q propagation delay MR to Q, Q propagation delay RS to Q, Q output transition time trigger pulse width A = HIGH B = LOW tW master reset pulse width HIGH clock pulse width RS; HIGH or LOW minimum output pulse width Q = HIGH, Q = LOW retrigger time A, B external timing resistor external timing capacitor removal time MR to A, B 70 14 12 80 16 14 - - - 19 7 6 25 9 7 275 100 80 - - - - - - - - - 90 18 15 100 20 17 - - - - 105 21 18 120 24 20 - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns - - - - - - - - - - - - 70 14 12 +25 TYP 77 28 22 61 22 18 83 30 24 19 7 6 17 6 5 MAX 240 48 41 185 37 31 250 50 43 75 15 13 - - - - - - - - - - - - - - - 90 18 15 -40 to +85 MIN MAX 300 60 51 230 46 39 315 63 54 95 19 16 - - - -40 to +125 MIN - - - - - - - - - - - - 105 21 18 MAX 360 72 61 280 56 48 375 75 64 110 22 19 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
74HC/HCT5555
TEST CONDITION VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.6
tPLH/tPHL
Fig.7
tPLH/tPHL
Fig.8; note 1
tTHL/tTLH
Fig.6
tW
Fig.6
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
Fig.7
tW
- - - - - -
Fig.8
tW
Fig.6; note 1
trt
- - - 5 1 50 50 120 24 20
0 0 0 - -
- - - 1000 1000
- - - - -
- - - - - - no limits
- - - - -
- - - - - -
ns ns ns k k pF pF
2.0 4.5 6.0 2.0 5.0 2.0 5.0 2.0 4.5 6.0
Fig.10; note 2
REXT
Fig.13
CEXT trem
Fig.13 Fig.7
39 14 11
- - -
150 30 26
- - -
180 36 31
- - -
ns ns ns
September 1993
10
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
Tamb (C) SYMBOL PARAMETER MIN fmax maximum clock pulse frequency maximum clock pulse frequency 2 10 12 6 30 35 +25 TYP 5.9 18 21 24.8 75 89 MAX - - - - - - -40 to +85 MIN 1.8 8 10 4.8 24 28 MAX - - - - - - -40 to +125 MIN 1.3 6.6 8 4 20 24 MAX - - - - - - MHz MHz MHz MHz MHz MHz UNIT
TEST CONDITION VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.8; note 3
fmax
Fig.9; note 4
Notes 1. One stage selected. 2. It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period exceeds the clock input cycle time divided by 2. 3. One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the RS clock input. 4. One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of the RS clock input.
September 1993
11
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: non-standard; bus driver with extended specification on VOH and VOL ICC category: MSI. Tamb (C) SYMBOL PARAMETER +25 - -40 to +85 - -0 to +125 MIN 4.4 - UNIT V CC (V) MAX V 4.5
74HC/HCT5555
TEST CONDITION VI OTHER Io = -20 A
MIN TYP MAX MIN MAX VOH HIGH level output voltage Q and Q outputs HIGH level output voltage Q and Q outputs HIGH level output voltage Q and Q outputs LOW level output voltage Q and Q outputs LOW level output voltage Q and Q outputs LOW level output voltage Q and Q outputs 4.4 4.5 4.4
VOH
3.98 4.32 -
3.84 -
3.7
-
V
4.5
Io = -6 mA
VOH
3.3
-
-
3
-
2.7
-
V
4.5
Io = -20 mA
VOL
-
0
0.1
-
0.1
-
0.1
V
4.5
Io = 20 A
VOL
-
0.15 0.26
-
0.33
-
0.40
V
4.5
Io = 6 mA
VOL
-
-
0.9
-
1.14
-
1.34
V
4.5
-
Io = 20 mA
September 1993
12
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
Tamb (C) SYMBOL PARAMETER +25 3.98 - - -40 to +85 3.84 - -0 to +125 MIN 3.7 - UNIT V CC (V) MAX V 4.5
TEST CONDITION VI RS = GND; OSC CON = VCC RS = VCC; OSC CON = GND; untriggered RS = VCC; OSC CON = VCC RS = VCC; OSC CON = GND; untriggered RS = VIH; OSC CON = VIH RS = VCC; OSC CON = VCC RS = VCC; OSC CON = VCC RS = VIL; OSC CON = VIL; untriggered OTHER Io = -2.6 mA
MIN TYP MAX MIN MAX VOH HIGH level output voltage RTC output
3.98 -
-
3.84 -
3.7
-
V
4.5
Io = -0.65 mA
4.4
4.5
-
4.4
-
4.4
-
V
4.5
Io = -20 A
4.4
4.5
-
4.4
-
4.4
-
V
4.5
Io = -20 A
VOH
HIGH level output voltage CTC output LOW level output voltage RTC output LOW level output voltage CTC output
3.98 -
-
3.84 -
3.7
-
V
4.5
Io = -3.2 mA
-
-
0.26
-
0.33
-
0.4
V
4.5
Io = 2.6 mA
VOL
-
0
0.1
-
0.1
-
0.1
V
4.5
Io = 20 A
VOL
-
-
0.26
-
0.33
-
0.4
V
4.5
Io = 3.2 mA
Notes 1. The RS input has CMOS input switching levels. 2. The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the following table. UNIT LOAD COEFFICIENT INPUT MR A B RTR/RTR OSC CON S0 - S2 S3 September 1993 13 UNIT LOAD COEFFICIENT 0.35 0.69 0.50 0.35 1.20 0.65 0.40
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER MIN tPLH/tPHL propagation delay A, B to Q, Q propagation delay MR to Q, Q propagation delay RS to Q, Q output transition time trigger pulse width A = HIGH B = LOW master reset pulse width HIGH clock pulse width RS; HIGH or LOW minimum output pulse width Q = HIGH, Q = LOW retrigger time A, B external timing resistor external timing capacitor removal time MR to A, B maximum clock pulse frequency maximum clock pulse frequency - +25 TYP 28 MAX 48 - -40 to +85 MIN MAX 60 -40 to +125 MIN - MAX 72 ns UNIT
74HC/HCT5555
TEST CONDITION VCC (V) 4.5 WAVEFORMS Fig.6
tPHL/tPLH
-
24
41
-
51
-
62
ns
4.5
Fig.7
tPHL/tPLH
-
32
54
-
68
-
81
ns
4.5
Fig.8; note 1
tTHL/tTLH tW
- 21
7 12
15 -
- 26
19 -
- 32
22 -
ns ns
4.5 4.5
Fig.6 Fig.6
tW
14
5
-
18
-
21
-
ns
4.5
Fig.7
tW
16
9
-
20
-
24
-
ns
4.5
Fig.8
tW
-
100
-
-
-
-
-
ns
4.5
Fig.6
trt REXT CEXT trem fmax
- 1 50 24 10
0 -
- 1000
- -
- - no limits
- -
- -
ns k pF
4.5 4.5 4.5 4.5 4.5
Fig.10; note 2 Fig.13 Fig.13 Fig.7 Fig.8; note 3
14 18
- -
30 8
- -
36 6.6
- -
ns MHz
fmax
30
75
-
24
-
20
-
MHz
4.5
Fig.9; note 4
September 1993
14
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
Notes 1. One stage selected.
74HC/HCT5555
2. It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period exceeds the clock input cycle time divided by 2. 3. One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the RS clock input. 4. One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of the RS clock input.
September 1993
15
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
AC WAVEFORMS
74HC/HCT5555
handbook, full pagewidth
tW 90% B INPUT 10% VM (1)
90% A INPUT GND 10% tW t THL Q OUTPUT t PHL t PLH Q OUTPUT VM (1) 10% t TLH t THL
MGA653
VM (1)
t TLH 90%
VM (1) 10% tW 90%
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the triggering of the delay timer by input A or B, the minimum pulse widths of the trigger inputs A and B, the output pulse width and output transition times.
September 1993
16
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
handbook, full pagewidth
MR INPUT
VM (1) tW
t rem
(1)
A INPUT
VM
t rem
B INPUT t PLH
VM (1)
Q OUTPUT
VM (1) t PHL
Q OUTPUT
VM (1)
MGA652-1
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the master reset (MR) pulse width, the master reset to outputs (Q and Q) propagation delays and the master reset to trigger inputs (A and B) removal time.
September 1993
17
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
handbook, full pagewidth
1/f max
RS INPUT
1
2 VCC
t PHL VM (1)
tW
Q OUTPUT
t PLH Q OUTPUT VM (1)
MGA651
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and the maximum clock frequency.
handbook, full pagewidth
1/f max
RS INPUT
VM (1) t PHL
Q OUTPUT
VM (1)
t PLH VM (1)
MGA654
Q OUTPUT
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9
Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and the maximum clock frequency (Output waveforms are not synchronized with respect to the RS waveform).
September 1993
18
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
handbook, full pagewidth
A INPUT tW B INPUT t rt Q OUTPUT tW tW tW
MGA650
tW
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Output pulse control using retrigger pulse (RTR/RTR = HIGH).
September 1993
19
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
APPLICATION INFORMATION
74HC/HCT5555
handbook, halfpage g
14 max. 12
MBA333
fs (mA/V)
handbook, halfpage
R bias = 560 k 10 VCC 8
typ.
0.47 F vi (f = 1 kHz)
input
output 100 F 6 A io GND
MGA645
min.
4 2
0
1
2
3
4
5 VCC (V)
6
Fig.11 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see Fig.12) and MR = LOW.
Fig.12 Typical forward transconductance gfs as a function of the supply voltage at VCC at Tamb = 25 C.
105 handbook, halfpage f osc (Hz) 10 4 Ct Rt
MGA647
handbook, halfpage
MR (from logic)
1 RS 103 R TC 2 C2 R2 Rt
MGA646
C TC 3 Ct
102
10 103 10 - 4
104 10 - 3
R t ( ) 106 105 10 - 2 C t ( F) 10 - 1
Typical formula for oscillator frequency:
1 f osc = ------------------------------2.5 x R t x C t
Ct curve at Rt = 100 k; R2 = 200 k. Rt curve at Ct = 1 nF; R2 = 2 x Rt. RC oscillator frequency as a function of Rt and Ct at VCC = 2 to 6 V; Tamb = 25 C.
Fig.13 Application information.
Fig.14 Example of an RC oscillator.
September 1993
20
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
Timing Component Limitations The oscillator frequency is mainly determined by RtCt, provided R2 2Rt and R2C2 << RtCt. The function of R2 is to minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance C2 should be kept as small as possible. In consideration of accuracy, Ct must be larger than the inherent stray capacitance. Rt must be larger than the "ON" resistance in series with it, which typically is 280 at VCC = 2 V, 130 at VCC = 4.5 V and 100 at VCC = 6 V. The recommended values for these components to maintain agreement with the typical oscillation formula are: Ct > 50 pF, up to any practical value, 10 k < Rt < 1 M. In order to avoid start-up problems, Rt >> 1 k. Typical Crystal Oscillator In Fig.15, R2 is the power limiting resistor. For starting and maintaining oscillation a minimum transconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 k. Above 14 MHz it is recommended replacement of R2 by a capacitor with a typical value of 35 pF. Accuracy Device accuracy is very precise for long time delays and has an accuracy of better than 1% for short time delays (1% applies to values 400 ns). Tolerances are dependent on the external components used, either RC network or crystal oscillator. Start-up Using External Clock The start of the timing pulse is initiated directly by the trigger pulse (asynchronously with respect to the oscillator clock). Triggering on a clock HIGH or clock LOW results in the following: * clock = HIGH; the timing pulse may be lengthened by a maximum of tW/2 (tW = clock pulse width) * clock = LOW; the timing pulse may be shortened by a maximum of tW/2 (tW = clock pulse width). This effect can be minimized by selecting more delay stages. When using only one or two delay stages, it is recommended to use an external time base that is synchronized with the negative-edge of the clock. Start-up Using RC Oscillator The first clock cycle is 35% of a time period too long. This effect can also be minimized by selecting more delay stages. Start-up Using Crystal Oscillator A crystal oscillator requires at least two clock cycles to start-up plus an unspecified period (ms) before the amplitude of the clock signal increases to its expected level. Although this device also operates at lower clock amplitudes, it is recommended to select the continuously running mode (OSC CON = HIGH) to prevent start-up delays.
74HC/HCT5555
Termination of the Timing Pulse The end of the timing pulse is synchronized with the falling edge of the oscillator clock. The timing pulse may lose synchronization under the following conditions: * high clock frequency and large number of stages are selected. This depends on the dynamic relationship that exists between the clock frequency and the ripple through delay of the subsequent stages. Synchronization When frequencies higher than those specified in the Table 'Synchronization limits' are used, the termination of timing pulse will lose synchronization with the falling edge of the oscillator. The unsynchronized timing pulse introduces errors, which can be minimized by increasing the number of stages used e.g. a 20 MHz clock frequency using all 24 stages will result in a frequency division of 16 777 225 instead of 16 777 216, an error of 0.0005%. The amount of error increases at high clock frequencies as the number of stages decrease. A clock frequency of 40 MHz and 4 stages selected results in a division of 18 instead of 16, a 12.5% error. Application example: * If a 400 ns timing pulse was required it would be more accurate to utilize a 5 MHz clock frequency using 1 stage or a 10 MHz clock frequency using 2 stages (due to synchronization with falling edge of the oscillator) than a 40 MHz clock frequency and 4 stages (synchronization is lost).
September 1993
21
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
Minimum Output Pulse Width The minimum output pulse width is determined by the minimum clock pulse width, plus the maximum propagation delay of A, B to Q. The rising edge of Q is dominated by the A, B to Q propagation delay, while the falling edge of Q is dominated by RS to Q propagation delay. These propagation delays are not equal. The SYNCHRONIZATION LIMITS NUMBER OF STAGES SELECTED 1 2 3 4 5 6 7 8 . 17 18 19 20 21 22 23 24 18 MHz 14 MHz 11 MHz 9.6 MHz 8.3 MHz 7.3 MHz 6.6 MHz 6 MHz . 3.2 MHz 3.0 MHz 2.9 MHz 2.8 MHz 2.7 MHz 2.6 MHz 2.5 MHz 2.4 MHz RS to Q propagation delay is some what longer, resulting in inaccurate outputs for extremely short pulses. The propagation delays are listed in the section 'AC Characteristics'. With these numbers it is possible to calculate the maximum deviation (an example is shown in Fig.16). Figure 16 is valid for an external clock where the trigger is synchronized to the falling edge of the clock only. The
74HC/HCT5555
graph shows that the minimum programmed pulse width of 100 ns is: * minimum of 4% too long * typically 7% too long * maximum of 10% too long.
CLOCK FREQUENCY (TYPICAL)
September 1993
22
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
handbook, halfpage
MR (from logic)
1
RS R TC R bias 100 k to 1 M 2
R2 2.2 k
C3
22 to 37 pF
C2
100 pF
MLB336
Fig.15 External components configuration for a crystal oscillator.
handbook, full pagewidth
40
MGA648
deviation (%)
36 32 28 24 20 16 12 8 4 0 0 100 200 300 400 500 programmed time (ns) 600 max. expected typ. expected min. expected
Fig.16 Graphic representation of short time delay accuracy; one stage selected; VCC = 4.5 V.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
23

▲Up To Search▲

Price & Availability of 74HCHCT5555

	To Download 74HCHCT5555 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .